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XMEGA A [MANUAL]
8077I–AVR–11/2012
5.14.8 SRCADDR0 – Source Address register 0
SRCADDR0, SRCADDR1, and SRCADDR2 represent the 24-bit value SRCADDR, which is the DMA channel source
address. SRCADDR2 is the most significant byte in the register. SRCADDR may be automatically incremented or
Bit 7:0 – SRCADDR[7:0]: Channel Source Address byte 0
These bits hold byte 0 of the 24-bit source address.
5.14.9 SRCADDR1 – Channel Source Address register 1
Bit 7:0 – SRCADDR[15:8]: Channel Source Address byte 1
These bits hold byte 1 of the 24-bit source address.
5.14.10 SRCADDR2 – Channel Source Address register 2
Bit 7:0 – SRCADDR[23:16]: Channel Source Address byte 2
These bits hold byte 2 of the 24-bit source address.
5.14.11 DESTADDR0 – Channel Destination Address register 0
DESTADDR0, DESTADDR1, and DESTADDR2 represent the 24-bit value DESTADDR, which is the DMA channel
destination address. DESTADDR2 holds the most significant byte in the register. DESTADDR may be automatically
Bit 7:0 – DESTADDR[7:0]: Channel Destination Address byte 0
These bits hold byte 0 of the 24-bit source address.
Bit
7
654
32
10
+0x08
SRCADDR[7:0]
Read/Write
R/W
Initial Value
0
000
00
Bit
7
65
43
2
1
0
+0x09
SRCADDR[15:8]
Read/Write
R/W
Initial Value
0
Bit
765
43
21
0
+0x0A
SRCADDR[23:16]
Read/Write
R/W
Initial Value
000
00
0
Bit
765432
10
+0x0C
DESTADDR[7:0]
Read/Write
R/W
Initial Value
000000
00